A field effect transistor (FET) using a compound semiconductor such as GaN, having excellent high-frequency characteristics, is widely in practical use as a semiconductor device operating in a microwave band.
The FET has, for example, the following structure, as disclosed in Japanese Patent Application National Publication No. 2007-537594. A rectangular source electrode and a rectangular drain electrode are formed, spaced from each other, on an operating layer on a semiconductor substrate. Between the source electrode and the drain electrode, a band-like gate electrode is formed. On the operating layer, a first insulation film is formed between the source electrode, the gate electrode and the drain electrode. On the first insulation film, a second insulation film is formed so as to cover the gate electrode. In a region from a top of the source electrode to a top of the second insulation film, a source field plate electrode is formed. The source field plate electrode is formed from the top of the source electrode to a vicinity of the drain electrode. On the source field plate electrode and between the source field plate electrode and the drain electrode, a third insulation film is formed.
According to the FET, formation of the source field plate electrode can lower a potential increased locally at a drain electrode side end portion of the source electrode. Hence, the FET capable of applying a high voltage can be achieved. However, since an interval between the source field plate electrode and the drain electrode is small, a high voltage is applied to the third insulation film formed between the source field plate electrode and the drain electrode. At this time, the third insulation film is damaged, which poses a problem of degradation in FET performance. Therefore, it is very important to form a source field plate electrode so that a distance between the source field plate electrode and the drain electrode is as designed, that is, to form the source field plate electrode to have a designed length.
As a method for forming the source field plate electrode to have a designed length, the following method is known, as disclosed in Japanese Patent Application Laid-Open No. 10-135239. The method is for metal vapor deposition using a resist layer having an overhang opening in forming a source field plate electrode of a semiconductor device.
As described above, by metal vapor deposition using the resist layer having the overhang opening, metal vapor-deposited in the opening and metal vapor-deposited on the resist layer can be spaced from each other. Hence unnecessary metal vapor-deposited on the resist layer can also be removed when removing the resist layer. Accordingly, no unnecessary metal is left on the field plate electrode, which allows the field plate electrode having the designed length to be formed.
However, in performing metal vapor deposition using the resist layer having the overhang opening in this way, there is formed a gap between an end portion of the source field plate electrode and a side wall of the opening in the resist layer, and therefore a deposited metal component diagonally entering the opening and metal deposited in the opening may flow into the gap, which generates a thin trailing portion at the end of the source field plate electrode. Accordingly, conventionally, when the trailing portion is formed, the distance between the source field plate electrode and the drain electrode is shortened and thus the third insulation film is damaged, which poses a problem of degradation in FET performance.